`include "defines.v"
`timescale 1ns / 1ns
module ex_mem(
    input wire clk,
    input wire rst,
    //from ex module
    input wire[`MemAddrBus] raddr_i,
    input wire[`MemAddrBus] waddr_i,
    input wire[`MemBus] wdata_i,
    input wire we_i,
    //input wire[7:0] test_input_i,
    // to ex
    output reg[`MemBus] rdata_o
);

        
    reg[`MemBus] _ram[0:`MemNum - 1];

    always @ (posedge clk) begin
            if (rst == `RstDisable && we_i == `WriteEnable)
                begin
                    _ram[waddr_i[31:2]] <= wdata_i;
                end

        end

    always @ (*) begin 
        if (rst == `RstEnable)
            rdata_o = `ZeroWord;
        else
            begin 
                rdata_o = _ram[raddr_i[31:2]];
            end


    end
endmodule